Low Power dissipation of 14-bit Pipelined ADC with Operational Amplifier

The design of 14 bit pipeline ADC has been carried out in the proposed research work by using TSMC 018μm technology. The design is implemented in LT SPICE SWICHER CAD -III Schematic Editor and the results are verified with LT spice and simulation is viewed in LT SPICE. The key design module is summarized here. 3-TIQ comparator is worn in the single stage of ADC. An analog multiplexer is used as DAC. An OPAMP has been used in analog adder. A unity gain inverting amplifier is designed by using an OPAMP for sample and hold circuit. An analog adder is designed by using OPAMP. Shift register has also been designed by using D flip-flop.