Design and Simulation of FinFET Circuits at Different Technologies

Power dissipation and propagation delay are the main barriers in the progress of electronics industry as it leads toward the Nanoscale regime of transistor and mainly transistor performance is degrade by subthreshold leakage current. Extreme level of transistor scaling is not ultimate solution for better electronics devices because it introduces short channel effects (SCE) when transistor scaled down below 16nm. To improve the performance of electronic circuits, researchers innovates a new transistor which is known as FinFET. FinFET is improved version of CMOS transistor with less power dissipation and propagation delay. This paper presents the different FinFET circuits and simulating these circuits using cadence virtuoso tool containing ASAP7 PDK and PTM models. Firstly, various FinFET leakage reduction circuits are simulated at different technologies and secondly the basic inverter, OAI and AOI circuits are analyzed. At last, a complete analysis of circuits using basic performance parameters like power dissipation and propagation delay are performed. From various simulation results, it can be concluded that FinFET transistor are more efficient and provides less power dissipation and propagation delay.