Research on XDMA High-Speed Data Transmission Architecture Based on PCIe

As part of the signal processing board based on hardware acceleration, this article mainly discusses how to achieve high-speed data transmission architecture between FPGA and PC through Scatter-Gather DMA based on the PCI Express bus. First, the characteristics and protocols of the PCIe bus, as well as the principles and implementation methods of SG DMA, are analyzed in detail. Then, the XDMA IP core was configured and generated in VIVADO. The IP core fully implements the functions of the transaction layer, physical layer, and data link layer of the PCIe protocol. This paper completes a transmission test platform based on Xilinx Kintex XC7k325T FPGA. It can read and write DDR3 and measure speed through PCIe. At the same time, transmission architecture and simulation are proposed. In addition, the XDMA driver is written based on Xilinx's official XDMA driver Answer_65444, which can realize the real-time communication between the PC and FPGA. On this basis, the PCIe write rate can reach 795MB/s, and the read rate can reach 637MB/ s.