Actively Compensated Read Assist Technique for 0.6 V Operation of 16 Mb High Density SRAM in 65nm LSTP

With the growing need for low power devices, low voltage operation becomes a key requirement. As the devices are operated at lower voltages, the functionality of the SRAM cell gets compromised. The SRAM cell stability becomes vulnerable to process variations at lower technology nodes. To enable memory operation, read assist is required. However, applying read assist across all corners degrades memory performance. Therefore, a process compensated read assist is required. First, we designed a process monitoring circuit whose output voltage varies with change in PVT. This output activates a read assist circuit to improve the Read Static Noise Margin (RSNM) of 6T SRAM cell whenever it falls below 6σ. At FNSP/125°C, read assist is required at 0.74V, whereas at SNSP and SNFP corners, read assist is not required. At slow corners, cell current is improved by 58% resulting in no loss in speed of operation of bitcell.