optimization for Interconnection Design in Deep Submicron Integrated Circuit

With the continuous reduction of device size, layout routing has become an important factor affecting the performance and reliability of the chip, especially in consumer electronics. Good routing optimization can obtain good chip delay performance in the last step of physical design. In this paper, interconnection based on deep submicron is studied in depth. The routing is analyzed from the perspectives of line width, line spacing and topology, and then verified by the physical simulation of layout. Finally, the results are illustrated by an operational amplifier case. This paper provides design and implementation reference for digital & analogical mixing integrated circuit designer in solving wiring.