Gain Enhancement Technique for On-Chip Monopole Antenna

This paper introduces a gain enhancement technique for monolithically integrated monopole antennas. The proposed configuration has been designed in a standard 0.13 μm SiGe BiCMOS process. The gain improvement was achieved by combining the on-chip monopole antenna with some parasitically coupled Split Ring Resonators (SRRs). The size of the SRR was firstly fixed to adapt their length to the monopole geometry while their resonant frequency was fine-tuned by using a capacitive load which serves to control the resonance frequency without changing their length. Thanks to this solution, it was possible to achieve a gain improvement of about 1 dBi with respect to an unloaded monopole. An experimental assessment showed a maximum measured antenna gain of 1.61 dB at 81.5 GHz and the antenna maintains good performance from 77 to 87 GHz.