A 38-GHz High Linearity and High Efficiency Power Amplifier for 5G Applications in 65-nm CMOS

A 38-GHz high linearity and high efficiency power amplifier is implemented in 65-nm CMOS process. To improve the back-off efficiency, transistors of the driver stage are biased in deep class-AB. Insertion loss from output stage matching is only 1 dB, resulting in high efficiency. A two-stage common source PA is designed to provide enough gain. This PA achieves a 20.5-dB small-signal gain, 14.6-dBm PSAT, 35.8% peak power-added efficiency (PAE), 13.1-dBm P1dB, and 30.1% PAE1dB. The linearity, which is measured in error vector magnitude (EVM) of 64-QAM with 250 MHz bandwidth, is better than -25 dB, at the power level of 10.1-dBm output power with 17% PAE. The chip size including all pads is 0.2964 mm
²
.