A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry

This paper presents a THD improved SAR ADC without any calibration or DEM for DAC mismatch. The proposed SAR ADC has a new method of cancellation of all even order distortions caused by a DAC mismatch. In order to improve THD performance, we focused on symmetric property in the DAC mismatch. This method just needs very simple circuits with a few extra clocks.

I. Introduction

For ADCs in the field of industrial robots, low latency, high SNDR (> 85 dB) and wide bandwidth (> 0.5 MHz) are required for the feedback control. Although incremental ADC[1] has inherently high linearity and high DR (dynamic range), a high DC gain amplifier is necessary for the integrator. By contrast, SAR ADC is a very simple architecture, so it is suitable for lower supply voltage and fine process. However, it is hard to realize high SNDR due to DAC mismatch, especially in upper bits. In fact, many SAR ADCs have a large input capacitance for mismatch suppression, which is often much higher than the kT/C noise requirement. Thus, calibration methods have been used in the conventional high-precision SAR ADCs. Many types of foreground[2] and background[3] calibrations are widely used for SAR ADCs, but they need a lot of memory cells and complex calculating engines for calibrating the DAC elements. To improve THD performance without calibration, we propose a new architecture focused on symmetric property in the DAC mismatch.