A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment

A 100-Gb/s continuous time linear equalizer (CTLE) for four-level pulse-amplitude modulation (PAM-4) in a 28-nm CMOS process is presented. The proposed CTLE provides peaking at Nyquist frequency, as well as peaking at mid-frequency for low-frequency channel-loss compensation. In addition, this design offers a coarse-fine tuning gain adjustment. The dc gain covers a wide range from -9dB to 12 dB with step size of less than 0.3 dB, and the peaking gain at Nyquist frequency can be adjusted from -3.4dB to 20 dB with a step size of less than 1.2 dB. The CTLE consumes 54-mW from a 0.9-V supply.