Stacked Nanosheet Based Reconfigurable FET

In this paper, we present a vertically stacked (VS) nanosheet (NS) FET architecture that can realize device reconfigurability and inverter action at the device level of operation. NS are uniformly n
⁺
and p
⁺
doped regions as in the junctionless device, which then is combined with the stacked silicides at the drain end to perform complimentary operation. A single gate with gate-all-around (GAA) architecture provides improved electrostatic integrity. With proper biasing, the device operates as nFET and pFET, respectively. Further, the impact of gate length (L
_g
) and NS thickness scaling on device characteristics are also analyzed. We observe that at reduced NS thickness, much improved OFF-state device characteristics along with the sharp transition in voltage transfer characteristic (VTC) curve is obtained, due to efficient gate control of the channel region.