Supply Induced Jitter-Aware Method for SSO (Simultaneous Switching Noise) for Multiple IPs Integrated in Single Package Substrate

This paper provides supply-induced jitter-aware sensitivity and systematic modeling approach for analyzing supply noise induced timing jitter in multiple IPs (intellectual property) high speed interface circuits integrated in one 1-2-14L FCCSP package substrate to perform the jitter generated by the supply noise in the time domain compared to present general analysis methods. During product design phase, IP integration effort takes place very first to define the package floor plan and then this floor structure will be used for mother board design. We propose an efficient method during IP integration for verification plan for timing budget calculation when IPs work simultaneously in a single package substrate at early design stage. The goal is to provide adequate performance for cost-effective and system solution and achieving on system-level success.