Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization

We propose a framework to co-optimize Yield along with Power, Performance and Area (PPA) through the design flow from logic synthesis through placement and routing (APR). We accomplish this by learning from silicon using a combination of test/diagnosis, inline/metrology and Failure Analysis (FA) results to create predictive models using Machine Learning (ML) techniques that are then used during design. Simulation results across three different CPU and Graphics cores show promising results with projected yield improvements of 11-17% with no area and performance / timing penalty with respect to design targets but with tradeoffs to both static and dynamic power. Better joint exploration of the PPA space along with yield indicates it is possible to recover yield with close to iso-PPA with respect to design targets. Pre-silicon results show ~10.4% yield increase with iso-area and -iso-performance and ~1% power penalty on a processor core.