Optimization of High Precision SAR ADC Used in the Remote Sensing Technology

This paper presents a novel method to calibrate the mismatch in the process of analyzing the acquired information by remote sensing technology. Moreover, the essence of reducing mismatch is the correction of analog-to-digital converters (ADCs). The proposed 12-bit successive approximation register (SAR) ADC uses the Vcm-Based structure to reduce the significant power from the most significant bit (MSB), and calibrates the mismatch in the capacitive array through sorting capacitors. The proposed ADC is implemented in the 180nm complementary metal-oxide-semiconductor (CMOS) technology and improves the spurious-free dynamic range (SFDR) from 62.59dB to 78.16dB and the signal-to-noise-distortion ratio (SNDR) from 58.356dB to 70.04dB.