Design of the Convolution Layer Using SoC FPGA and Evaluation of Latency Using a Camera Signal

In recent years, deep learning has been applied to various problems such as image recognition, voice recognition, and natural language processing, and has achieved results. At the same time, it is used in various applications and fields and is expected to be used in embedded systems such as IoT devices. However, deep learning requires a large computational cost, generally requires a GPU, and it is difficult to implement on small embedded devices. Also, in recent years, FPGAs have been applied to image processing technology fields such as defect inspection of automobiles, security systems, and industrial products. Hardware acceleration is one of the techniques to improve processing speed and it is often used in the field of image processing. In this work, the hardware acceleration for the convolutional neural network was designed compared to software processing. The hardware-based convolutional layer shows high performance than the software-based design. Additionally, these hardware-based modules were implemented on FPGA. In this paper, we show the detail of the architecture and the comparison result of processing time with CPU.