An FPGA based real-time radar target simulator with high spur suppression

Radar target simulators have been widely used in accelerating radar performance testing. The real-time performance and signal quality of the echo signal are important criteria for evaluating the target simulator, and SFDR is an important indicator for evaluating the signal quality. The traditional target simulator adopts the form of target playback with poor real-time performance, and cannot effectively suppress spurs in the baseband signal processing, which affects the signal quality. Therefore, this paper introduces a FPGA-based low-spur real-time target echo simulator. That suppress phase spurs by generating m sequences, realizing real-time simulation using link deterministic delay and FPGA parallel structure. The high-signal-quality real-time echo generated by this device can make up for the defects of the traditional simulator and achieve high-precision and high-quality radar testing. Simulations validate that the proposed simulator can achieve real time echo simulation with high SFDR.