Advanced 22 nm FD-SOI devices integration platform

In this work, integration of 22 nm fully depleted silicon-on-insulator (FD-SOI) process with High-k first, metal gate last is demonstrated. The fabricated logic N-type MOSFET (NFET) and P-type MOSFET (PFET) show very good short channel effect (SCE) control. The logic NFET/PFET characteristics under different temperatures are measured and analyzed. Threshold voltage to temperature sensitivity is evaluated for using the back bias to tune device and get performance/power balance. The optimization of static noise margin of SRAM is also studied.