Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications

In this work, through calibrated simulations, comparative analysis of n-type Negative Capacitance (NC) Junctionless (JL) and Inversion Mode (IM) transistor is performed for Low Power (LP) applications. Through systematic metholdology and physical insights, it is highlighted that NC JL device exhbits negative internal gate voltage (V
_int
) at zero applied external gate bias (V
_gs
), which is benefical to achieve significantly lower value of off-current (I
_off
) than NC IM device for LP applications. It is demonstrated that negative V
_int
in NC JL device can further be utilized to lower the gate workfunction to mid-gap level while achieving the and I
_on
~ 1.3 mA/μm at lower I
_off
~ 10 pA/μm. The work showcases the opportunites to achieve the International Roadmap for Devices and Systems (IRDS) traget at gate length (L
_g
) of 20 nm and drain bias (V
_ds
) of 0.1 V for designing LP systems and circuits using NC JL transistor.