Partial Dynamic Reconfiguration for efficient Adaptive Implementation of a Video Shot Boundary Detection System

In this paper, we propose a dynamic implementation, on FPGA, of a video shot boundary detection system based on the Local Histogram descriptor (LH) and the Color Structure Descriptor (CSD). Different versions of these descriptors have been implemented: three versions of the CSD (32, 16 and 8 quantization levels) and two versions for the LH (8 and 4 quantization levels). The versions of the obtained hardware modules can be loaded according to the requirements of the application in different possible Partial Reconfigurable Region (PRR) in the FPGA circuit. The objective is to optimize the hardware resources by adapting each PRR to the size of the hardware task. A partitioning adapted to the different scenarios and versions of the implemented modules has been proposed. We have used the ZedBoard, which is a low-cost development board for the Xilinx Zynq-7000 SOC. A significant gain of hardware resources occupancy rate was obtained by this implementation.