A Novel High Performance Universal Measurement Logic Element

This paper proposes a novel universal measurement logic element. The proposed logic element can be used as counter for increment and decrement of operations, the same logic element can also be used as a 2 ’s complement (Negate) operation as well as priority encoder. These basic operations very often fall in the critical path of the data path and/or control path of the digital systems. For example, priority encoder in TCAM (Ternary Content Addressable Memory) based IP lookup and Packet Classification engine. Theoretical critical path delay of the proposed logic element is $O(log_{4}n)$. The proposed design reduces the critical path delay by 35.84%, 38%, 41% and energy per operation is reduced by the factor of 32%, 37.4%, 41.6% for 32-bit, 64-bit and 128-bit respectively compared to the recently reported work from the literature. Since, the critical subcomponent delay is reduced, the over all system delay also reduces by an appropriate factor.