Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology

The currently dominating CMOS based synchronous domain has reached a point where further advancement in terms of speed and size is becoming more and more challenging. CMOS devices in deep-submicron region encounter various technological limitations, while high speed clock management significantly adds to the design complexity. NULL Convention Logic (NCL) is a clockless approach, which eliminates clock-related issues faced in synchronous designs; and Carbon Nanotube Field Effect Transistor (CNTFET) technology is a promising alternative to counter the scaling limitations of CMOS technology. This paper presents various CNTFET based implementations of static NCL gates. The different designs are analyzed in terms of speed of operation, energy consumption, and leakage power dissipation, followed by a comparison with standard CMOS implementation.