A 5-GHz Phase Compensation Spread Spectrum Clock Generator for High Speed SerDes Application

In this paper, a phase compensated spread spectrum clock generator (SSCG) with triangular modulation profile is presented. The phase interpolator (PI) based on 32 phase selectors (PS) with wired-AND logic is proposed to implement phase interpolation. This structure has lower power consumption and no static current. The SSCG exhibits 630-fs and 640-fs rms jitter with SSC-off and SSC-on at 5-GHz, and EMI reduction is 18.97-dB under the down spread modulation of 5000-ppm. The power consumption of this design is 46.54mW. The design has been implemented in 55-nm CMOS process and occupies an area of 0.42×0.22 mm
²
.