Transforming Natural Language Specifications to Logical Forms for Hardware Verification

We propose a framework for extracting natural language assertions from hardware design specification documents. The entire parse tree of each input sentence in a design spec is viewed as a network of words connected to facilitate the creation of semantic frames. We employ a lexicalized grammar that associates words with both semantic and syntactic relations that assist in filling the slots in the semantic frames. At the same time, the accuracy of the extracted semantics is ensured by the incremental understanding algorithm that is guided by both syntactic and semantic rules of the hardware verification domain. We evaluated the framework by writing assertions taken from specification documents of the Memory controller, UART, and the AMBA ACE protocol. System Verilog Assertions (SVA) were automatically generated from logical expressions. Since accuracy is of paramount importance, whenever a complex sentence cannot be understood. we identify and report to the user.