BEOL Cu Gap-fill Performance Improvement for 14nm Technology Node

The continuous scaling in the logic device towards 14nm node dimensions has presented numerous engineering and manufacturing challenges in BEOL Cu interconnection. Small process marginality between the CuMn seed deposition and Cu plating processes is the primary source of voids in Cu interconnects. A chemical vapor deposited (CVD) cobalt liner was used as an enhance layer to replace conventional PVD Ta in 14nm technology node. This paper analyze cobalt property and present how Cu seed thickness (THK), Deposition combine Etch (DCE) ratio, AC bias power impact on defect and top opening of trench. Experiment result shown the defect between dense trench line area and SRAM area are quite tradeoff. Trench area requests bigger top opening, while SRAM area requests more Cu step coverage on sidewall. Defect mechanism was also detail discussed. Optimized parameters were finally presented and the defect level was significantly reduced. For more challenge structure wafer, A L9 Taguchi DOE was designed and the result show ECP MW current increase combine with start earlier can further benefit defect. Defect count almost free. The benefit was thought comes from Cu better nucleation capability at ECP process.