Improved HCI of Embedded High Voltage EDNMOS in Advanced CMOS Process

HCI is always a big concern for high voltage device and normally it can be improved by device size optimization, implant energy and dosage tuning. But in some case, this is not enough, especially for the embedded high voltage EDNMOS integrated in the advanced CMOS process. In this paper, we proposed an additional oxide layer under silicide block film and demonstrated the significantly improved HCI performance of one embedded high voltage EDNMOS, which failed HCI with traditional optimization on device size and implant process.