A Study of FinFET Device Optimization and PPA Analysis at 5 nm Node

Since the logic 5 nm node still uses FinFET device, it still has room for device performance improvement since its first debut in the production of 16 nm node. The goal of this paper is to investigate the FinFET device optimization and Power Performance Area (PPA) at the 5 nm node. We have simulated FinFET device electrical characteristics at Front-End-Of-the-Line (FEOL) with Technology Computer Aided Design (TCAD). We first focus on the device with different spacer thicknesses to investigate DC and AC characteristics. Then we focus on the power and speed performance of Ring Oscillator (RO) circuits based on 5 nm NMOS and PMOS devices. Detailed study has been carried out to analyze the influence of Number of fins (Nfin), Back-End-Of-the-Line (BEOL) interconnect length, and fan-out number to power and speed. We hope that our results can assist other researchers in better understanding of the 5 nm FinFET device performance.