Power Oriented CMOL Defect-Tolerant Mapping with Available Nanodevices

Due to the high defect rate of nano-technologies, the defect-tolerant mapping of CMOS/nanowire/molecular hybrid (CMOL) circuit becomes critical. In this paper, a simplified power consumption model is established first to guide the exploration of power-optimized mapping methods. Considering the additional energy loss caused by the activation of extra nanodevices during the process of tolerating stuck-at-close defects, a trim method is proposed to extract available nanodevices by bypassing defects on the CMOL array. Evolutionary algorithm (EA) is adopted to complete mapping. The experiment shows the proposed method has a better performance in power consumption with higher mapping speed.