Equivalent quantization correction technique for Pipelined SAR ADC

An equivalent quantization correction technique for the pipelined successive approximation register (PI-SAR) analog-to-digital converter (ADC) is proposed. The technique corrects both the capacitance mismatch and the residual amplifier (RA) gain errors. It utilizes the low capacitors to quantify the digital weight of each capacitor, and corrects the RA gain errors by the digital weight of capacitors. Based on a 14-bit 100MSs PI-SAR ADC with the calibration technique, the validity of the technique is fully verified. The implementation of the correction technique requires only simple control logic of analog circuit and adders along with multiplexers of digital circuit. The simulation results indicate that the proposed calibration technique enhances the performance of the ADC effectively. SFDR, SNDR improved from 53.33dB, 47.33dB to 102.21dB, 82.20dB, respectively. The digital circuit only contains 6162 gates and consumes 0.154mW.