A 20MS/s 12b 737.76μW SAR ADC in 0.18μm CMOS

A 20 MS/s, 12 bits SAR ADC with low power is proposed in this paper. Architectural redundancy, correlated reversed switching scheme (CRS) and segmented DAC technology are applied in this successive approximation ADC (SAR ADC) at the same time. Therefore, these mechanisms provide a better balance between speed and resolution, and pave the way for higher sampling rates and better power efficiency. Settling time, comparator delay and logic delay are the key factors which restrict the speed of ADC. To solve this problem, the SAR ADC adopts the asynchronous control logic, while the capacitor array which is reasonably split. The whole work is implemented on the 0.18 μm CMOS process. With the Nyquist frequency input, the SNDR and SFDR are 70.4 dB and 81.2 dB, respectively, and the ENOB is 11.40 bits. The power consumption of the SAR ADC is only 737.76 μW.