An Impedance Calibration Method Based on Temperature and Process Monitor for LPDDR5 Interface

The paper presents an impedance calibration technique based on the process and temperature compensation for the voltage-mode driver in the LPDDR interface. A new monitoring circuit is proposed and the impedance calibration procedure is achieved by detecting and compensating MOSFET process, resistor process and temperature variation. The voltage-mode driver with impedance calibration circuits is analyzed and designed in accordance with the JEDEC LPDDR5(Low Power Double Data Rate) standard. The proposed design is implemented with 14nm FinFET technology using 0.5V supply voltage. The average calibration accuracy of 1.09% and 1.92% can be achieved, respectively, in pull-up and pull-down networks with the impedance calibration circuit.