Self-optimizing Two-layer Network-on-Chip Based on Dominant Network-Flow Adaption

Network-on-Chip (NoC) is an important subsystem of multi-core system design, which can achieve low-latency, low-power, and high-bandwidth communication of data. According to earlier researches, communication between cores has the pattern that a part of flows can dominate network traffics, and it can be predicted by analyzing previous flows. In this paper, a two-layer NoC that employs an online machine learning algorithm to periodically construct predicting models at runtime and builds point-to-point paths between routers for dominant flows is implemented. A cluster-based architecture with all the cores in the same cluster sharing the same circuit-switching router is designed to reduce the number of flows. This architecture declines the complicity of flow analysis and increases the utilization of circuit-switching network. Several methods, such as data compression, are used to reduce the area and power consumption in the hardware design. Experimental results reveal that the proposed design for a 64-core system optimizes packet transmission latency as much as 40% and 18% under static and dynamic benchmarks respectively. Based on register-transfer level (RTL) model, the costs of the hardware design are evaluated. The results reveal that our work obtains latency optimization at the expense of small hardware costs.