A High Linearity T&H circuit for 1GHz Pipeline ADC in 65nm CMOS

A 3.3/2.5V/1.2V high linearity track-and-hold (T&H) circuit for 1GHz Pipeline analog to digital converter (ADC) in 65nm CMOS is implemented. It includes the two input buffer with source follower, bias and common mode voltage and generated part, input-impedance matching network and SPI part. Input-impedance matching network include a 50- Ω /100- Ω /200-Ω resistor controlled with SPI. The simulated results show that the SFDR and SNDR of the input buffer can get 89dB and 88dB, respectively. The power consumption is 158mW with typical 3.3V/2.5V/1.2V supply.