A New Approximate Adder with Duplicate-Constant Scheme for Energy Efficient Applications

This paper proposes a new approximate adder that significantly reduces area, power, and energy consumptions by exploiting a duplicate of lower-part inputs and a constant value while providing an acceptable computation accuracy. The proposed adder implemented in a 65-nm CMOS process reduces area, power, and energy by 46%, 49%, and 74%, respectively, over a traditional accurate adder. To evaluate the effectiveness of the proposed design, we apply it to the Gaussian filter and demonstrate that the approximation errors produced by our adder make a negligible impact on the output image quality.