Warpage Assessment of Chip Module in Chip Last FO-MCM Platform for Non-wetting Risk Evaluation

In recent years, semiconductor products have developed rapidly, from desktop computers with basic computing to Internet-connected smartphones, to emerging intelligent and perceived smart system products, such as mass-produced of smart home appliances ` smart watches, and under development of smart glasses. The product trend is toward high performance, multi-functional integration, thinner profile and lower cost features. These requirements are interrelated with wafer technology and assembly process development. The advanced wafer technology, such as 7nm / 5nm, will provide higher performance. However, as Moore's Law is approaching the physical limit, the industry has turned to the development of advanced packaging solution technologies to break through this bottleneck. At present, the industry's forward-looking packaging platform includes 2.5D ` 3D ` Fan-out (FO-MCM, FO-PoP, FO-WLCSP) and SiP modules, etc., which technologies can integrate chiplet ` chip stack ` passive components as heterogeneous integrated packaging solutions. Fan-Out MCM Platform has integrative characteristics for homogeneous / heterogeneous wafers and passives ` lower cost and lower profile advantage than 2.5D, also provided comparable performance to 2.5D by RDL design.In this study that will assess chip module warpage performance during reflow high temperature 245C of chip last FO-MCM, that is important for C4 bump non-wetting phenomenon when chip module bonding to substrate or directly SMT bonding to PCB. And it will consider factors include chip module floorplan, chip module size, chip module thickness, die gap size between die to die and RDL/PSV total thickness effect.