Multi-Function Scan Circuit

The practice of parallel computing emphasizes frequently used patterns. Some of them can be accelerated using appropriate networks of simple circuits. We propose a solution, based on the frame offered by the Beneš permutation network. It is adapted to efficiently accelerate some of the most used parallel computation patterns: prefix, split, reduction. The cells of the Beneš network associated to a Map pattern of n units are designed to support the additional functions. Two versions are considered: a log-depth pipelined version and a sequential, iterative version.