I/O Cells Latchup Immunity: Methodology for Compact Layout Rules in an Advanced CMOS Technology

A methodology for I/O cells area optimization starting from latch-up protection rules will be presented. To define compact layout rules, the starting points will be the design rule formally given by the foundry. The proposed methodology uses Design of Experiment (DOE) statistical approach based on the mentioned rules. The result will be a consistent flow that can be re-iterated for each silicon-implemented latchup test-chip, regardless of the technological node. The methodology will also help in finding the sensitivity of all input parameters in relationship to the tested output.