Improved Real Number Model Verification Using Post-Processed Analog Simulations

Electronic circuit development process involves many steps, including pre-silicon verification, which is too slow and lengthy for the electronic circuit market. The entire verification time can be greatly reduced by introducing behavioral modeling using real numbers. However, behavioral modeling engineers face the problem of long model verification time, mostly affected by the time consumed on schematic simulation. This paper presents a new methodology that uses Virtuoso environment, Cadence integrated scripting languages and high-level programming languages in order to achieve a considerable reduction in said verification time. This is accomplished through analog simulation post-processing done by the developed algorithms, whilst only requiring the digital engine for model's verification. Consequently, the analog engine is used only when the changes brought to the schematic circuit will determine a different circuit behavior.