Small-Signal Approach for Precise Evaluation of Gate Losses in Soft-Switched Wide-Band-Gap Transistors

High-frequency switching is favorable for fast transient response, small size of passive components and superior power density, especially in soft-switching topologies. At high frequencies, power dissipation due to consecutive charging/discharging of gate capacitance is considerably large. As presented in this work, the actual gate charge (Q
_G
) of a transistor can be very different from the typical values reported in manufacturer datasheet, which leads to errors in estimation and modeling of gate loss based on datasheets. Furthermore, the reported Q
_G
values in datasheets correspond to a hard-switching test condition, and are not a good representative of the losses in soft-switched transistors. Here, we propose a simple method to precisely evaluate gate loss in soft-switched transistors for high-frequency applications. A small-signal input-capacitance measurement is used to derive gate loss in two commercial Gallium-Nitride (GaN) transistors. The estimated losses are then verified by results from accurate thermal modeling based on a matrix of temperatures, when the transistors are driven up to 30 MHz. The results are of great significance to the modeling and accurate measurement of gate losses at high frequencies. It is instrumental to a proper cooling design to avoid device and gate driver thermal runaway and failure. Also, the more accurate gate capacitance measurement enables an accurate dead time adjustment to achieve synchronized turn ON between various transistors in soft-switching topologies.