Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol

We present a family of synthesizable standard-cell-based synchronization FIFOs for crossing between asynchronous and synchronous timing domains. These FIFOs are composed of modular mix-and-match components. The input and output interfaces are interchangeable for edge-triggered synchronous communication and for the as P* asynchronous pulse-based handshake protocol. The FIFO capacity, data width, synchronizer latency, and interface protocols are independent design parameters, allowing the FIFO to be easily configured for different requirements. The modular design makes the FIFO ideal for use in system-on-chip applications, where clock-domain crossing is required, or multiple clock domains communicate using an asynchronous network-on-chip. Our designs demonstrate high-throughput communication and hide most of the synchronization latency. The FIFOs are fully synthesizable using widely available standard-cell libraries and a standard ASIC design flow. We generate layouts for several different synchronous and asynchronous FIFOs. All instances can operate at speeds greater than 1.92 GHz under worst-case conditions when implemented in a 45nm CMOS process. The design flow and a fully parameterized Verilog implementation are released as an open-source library.