Transient Voltage Suppressor (TVS) on Signal Integrity of Microelectronics System with CMOS ICs under System-Level ESD Test

Transient voltage suppressor (TVS) has been widely used on the PCB to protect the microelectronics system against the system-level electrostatic discharge (ESD) events. However, the signal integrity of the system operations may be destroyed after the system-level ESD test, if the TVS was designed with a holding voltage lower than the operating voltage of CMOS ICs those equipped in the system. In this work, the signal integrity of microelectronics system protected by the TVS with different holding voltages was studied under the system-level ESD test. By monitoring the transient voltage waveforms in the time domain during system-level ESD test, the system malfunction has been found when the TVS is with a lower holding voltage. Therefore, the holding voltage of TVS must be greater than the system operating voltage to keep the well signal integrity in the applications.