Fault Injection Controller Based Framework to Characterize Multiple Bit Upsets for FPGA Designs

FPGA-based designs are more susceptible to soft errors compared to ASIC designs they contain more memory elements. In this paper, we focus on designing a fault injection framework for an FPGA based design and study the probability of Multiple Bit Upsets (MBUs) and the most vulnerable resource of an FPGA. Since the number of possible error sites in the digital design can be huge, we propose a two-step approach for fault injection. We first identify critical nodes in the design which can cause Multiple Bit Upsets and then feed this information as input to the FPGA based controller, that performs the Monte-Carlo analysis. This analysis selects a random error site for fault injection at a random clock cycle. The advantage of the proposed technique is that there is no need to re-program the FPGA for every error injected. The proposed framework has been tested on ISCAS'85 benchmark circuits configured on an Artix-7 FPGA. We find that the probability of Multiple Bit Flips (>3 bit upsets) is substantial (29.74% on average) in most circuits and the Flip-Flop is found to be the most vulnerable component in the FPGA.