Estimation of Power and Delay Parameters for Reconfigurable Decoders in SRAM by Selective Precharge Schemes

In this paper, a high speed 5-32-bit dynamic decoder of different styles are examined for different loads of memory blocks. The power dissipation, delay, frequency & VDD of various logic styles are evaluated and compared. Then, proposed the use of a dynamic decoder and reconfigurable decoder designs to save power and delay in memory access. These techniques have been applied to simulated models on two different technology nodes (180 nm and 350 nm) for low power CMOS technology by exploring multi-V
_DD
design space. The exploration of reconfigurable decoders design parameter variable capacitance load by number of stages, number of inputs, and its type of structure are presented.