Efficient LDPC Encoder Designs for Magnetic Recording Media

Low-Density Parity-Check (LDPC) codes are widely considered an advantageous option for forward error correction (FEC) on magnetic recording (MR) media. The vast majority of related research, however, has so far been focused on the analytical optimization of code design and algorithms. Although high-speed encoding and decoding with low hardware footprint are important for MR media, hardware implementations for such encoding schemes have so far been scarce. Among the proposed LDPC code variants, protograph-based codes are a promising option, because of their excellent performance characteristics and efficient implementation. In this work, we leverage the architecture of our previous work on LDPC encoders for space applications and we propose efficient encoder designs for the protograph-based LDPC codes proposed so far for MR media. The proposed designs are implemented in hardware as Field Programmable Gate Array (FPGA) accelerators. The efficiency of the introduced architectures is demonstrated on an FPGA development board, achieving multi-Gbps throughput, adequate for modern MR application standards.