Comparison of Parallel Prefix Adders Based on FPGA & ASIC Implementations

Two operand addition is an indispensable operation in almost every embedded system and DSPs (Digital Signal Processors). It is also considered as basic requisite for other arithmetic operations. However, there is always a trade-off among the speed, area and power dissipation of adders that determines the overall performance of the system. In the addition operation, the carry propagation being one of the performance issues puts a limit on its speed. Consequently, improvement in the speed along with reduction in covered area has been a continuous pursuit in VLSI (Very Large Scale Integration) system design. Parallel Prefix Adders (PPAs) are the best among the existing adders in terms of the area covered and the delay encountered. Hence, they are preferred choice for high performance adders of larger numbers. In this work, we have compared the FPGA and ASIC implementations of three Parallel Prefix Adders, namely Kogge-Stone, Ladner-Fischer, and Brent-Kung. The Artix-7 FPGA implementation has been done using Xilinx Vivado2018.2 suite, on the other hand, the ASIC implementation has been performed by Cadence Encounter tool. It is found that no single adder is rewarding for all the performance aspects (Power, Delay and Area). Rather, different adder is preferable over the other for different aspect, hence the adder is chosen according to the design requirement.