Switching Current Imbalance Mitigation for Paralleled SiC MOSFETs Using Common-mode Choke in Gate Loop

Paralleling SiC MOSFETs is a popular way to increase the current capacity. However, due to asymmetric layout, device parameter mismatch and other factors, imbalanced switching or dynamic current is observed among the paralleled switches in multi-device paralleling application which results in unequal switching loss, challenging the security and reliability of the system. In this paper, a common-mode choke in the gate loop is proposed and analyzed to suppress the imbalanced switching current induced by asymmetric layout in a half-bridge configuration with a Kelvin-source connection. The mechanism of the proposed method is comprehensively investigated to show that though the common-mode choke is placed in the gate loop, it can also mitigate the imbalanced current caused by asymmetric power loop. And it also shows that only the leakage inductance of the choke is seen in the gate loop and thus the switching speed is not expected to be influenced. The proposed method can be easily extended to multi-device paralleling application and the switching transients is hardly influenced by the common-mode choke. Simulation and experimental results are presented to verify the proposed method.