Influence of Paralleled SiC MOSFET on Turn-off Gate Voltage Oscillation

SiC MOSFET has been widely used in automotive and industry due to low on resistance and fast switching speed. Paralleled connection of SiC devices or modules is a cost-effective way to achieve high power application. A good static and dynamic current sharing of paralleled devices is always the top priority in circuit design. However, the device gate performance is usually been ignored. This paper addresses the influence of paralleled SiC MOSFETs on device turn-off gate voltage oscillation. The model of paralleled SiC MOSFETs system with detailed parasitic parameters is proposed. Driver signal delay and varied threshold voltage yield circulating current, which flows to driver source loop and power source loop. The circulating current in driver source loop brings source-gate voltage oscillation, which may damage the gate and device. The impact of AC layout and key parameters in drive and power circuits on turn-off gate voltage oscillation are proposed with simulation results. Finally, experimental results with five paralleled SiC MOSFETs are given.