A low power Charge Steering Based Frequency Divider

This paper presents a low-power charge steering based frequency divider. This divider is designed for wireless local area networks (WLAN) and the internet of things (IoT) applications. A non-return to zero low power latch is proposed with charge steering logic (CSL) instead of the current source of the conventional current mode logic (CML). Then a master-slave flip flop is implemented using CSL latch. A divide by two circuits is proposed and designed using a 130-nm CMOS process. The frequency divider power consumption at 2.4 GHz, which is the most used frequency band in the WLAN application, is 36 μW from a 1.2-V supply. The sensitivity curve for the proposed divider is also presented. A maximum frequency of 9.6 GHz is achieved with a self-oscillation frequency of 1 GHz.