Hardware Model for Efficient Edge Detection in Images

Reconfigurable algorithm for digital image processing is now a growing area of research in real time embedded systems. The Edge Detection Algorithms are one of the primary algorithms for object detection through segmentation and extraction in digital image processing. These algorithms are usually used in software but can also be implemented for special purposes in hardware including high processing speed and good accuracy. The limitation of the processor speed affects the software implementation of image processing algorithms. The advances in VLSI technology have solved this. This project uses the Hardware Description Language (HDL) to implement the Sobel edge detection algorithm for Field Programmable Gate Array devices (FPGA) and focuses on the outstanding features of FPGA technology. The analysis shows that the hardware Sobel edge operator implements provide a higher speed than the simulation software. The proposed implementation uses a modified architecture that reduces hardware resources effectively. The images are transmitted through serial UART communication from PC to FPGA computer.