Research On FOPLP Package of multi-chip Power Module

Power devices are developing for the small volume, high performance and modularization. With more and more application scenarios of Brushless Direct Current Motor (BLDC), MOSFET multi-chip module (MCM) is popular with people. However, the conventional wire Bonding and Copper clip welding technology struggles to meet the requirements for the excessive heat accumulation and complex logic problems in MCM. While the above problems can be well solved by using the new Fan out panel level packing(FOPLP) technology for QFN packaging of multi-chip. The traditional welding technology is used at the bottom of the chip, and the copper porous link is used at the top of the chip with low parasitic capacitance, inductance and low R
dson
in electrical performance. In respect to thermal management, the θ
JC
on the top of the chip can be reduced, which has the effect of double-sided heat dissipation. Top Layer interconnection technology is adopted in the packaging scheme, which can have complex circuit layout.This paper mainly describes the technical implementation of this packaging technology, adopting the finite element software to establish a three-dimensional model of a new type of FOPLP and wire welding packaging for MCM. The thermal resistance of different packaging schemes is calculated to confirm the advantages and disadvantages of different schemes by the way of thermal simulation, the internal temperature distribution of different packaging structures and the main influencing factors of the thermal resistance of packaging compared.