Cu pillar based Advanced Packaging, for large area & fine pitch heterogeneous devices

The continuous evolution of electronic devices has increased a serious concern on 2.5D and 3D advanced packaging. Applications in domains such as displays, automotive, defense or space, require large volumes of interconnects to cover large areas in order to achieve better performances for monolithic components. One of the main challenges of large surface interconnects for display applications, is the assembly control with a yield close to 100 % on the entire device surface.This must be guaranteed whatever the components shape, their positive or negative bow and warp or its interconnection pitch. The flip-chip based attachment technology using copper (Cu) pillars with tin solder family capping has become the mainstream process choice for fine pitch configurations. Moreover, the industrial supply chain for such kind of interconnections is today available in the packaging industry, however at much higher pitch than that we develop in Research and development level. With the increase of the die dimensions and the decrease of the pitch and bump diameters (higher resolution demand of the market), the associated number of interconnects per device is also increasing. Therefore, the manufacturing challenges in terms of bump height, Cu pillars field, bow and warp variations for such big dies, and the tin oxide issue management, have become extremely stringent. If the pillars are too short, too tall, have large height distribution, or inhomogeneous solder thickness to match the cumulated warpage of the assembly, we will have to face serious hybridization issues. Indeed, the solder during the reflow process will not wet properly the opposite pads or will flow over the copper pillar sides leading to electrical open or short failures. This finally will lead to a poor hybridization yield.The heterogeneity of the stacked materials used to build the active devices (Top dies with polymers, oxides, metals, semiconductors) highly complicates the control of the components behavior at the hybridization temperatures needed by the lead free solders. The same happens when increasing the interconnection area. Indeed, with high bow due to the internal mechanical stress induced by the heterogeneous nature of the components stack, and its resulting shape (concave or convex, or warped); the connections may be only effective at the borders of the sample. As the die attach pattern density becomes complex, sparse on a part of the surface (typically at the edge) and very dense on the other parts (typically in the center), assembly parameters due to such configuration of the devices becomes a big packaging challenge. In this paper, we present hybridizations with high wettability yield of surfaces around 4 cm
²
, Cu pillars-based on Silicon substrates with 500000 interconnects and compatible with high quality polymer underfilling without voids. The influence of different bow values, assembly parameters and techniques have also been investigated. A particular focus will be made on the extent of the characterizations. These promising results authorize the possibility to extend applications of Cu pillars to higher interconnect areas on monolithic devices with lower pitches.