Power Distribution Network Modeling and Design of Re-Distribution Layer in DDR Application

In this paper, the design tips considering power integrity (PI) for the power distribution network (PDN) in an re-distribution layer (RDL) are presented. First, the methodology of chip-RDL co-simulation is introduced. It indicates that decreasing the PDN loop inductance is critical for a robust PDN design in a high-speed transmission channel. Then, the loop inductance based on a simplified PDN model is derived, which reveals several possible ways to reduce the voltage ripple between power/ground terminals. Finally, the PDN design tips are proposed and verified based on the derived results. These design tips demonstrate that the PI issues of an RDL can be avoided at an early stage of the chip-package co-design.